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19-4302; Rev 2; 6/10
KIT ATION EVALU ABLE AVAIL
24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
General Description Features
Four Fully Differential Simultaneously Sampled Channels Cascadable for Up to 32 Channels of Simultaneous Sampling 106dB SNR at 16ksps 117dB SNR at 1ksps 0.25% Error Over a 1000:1 Dynamic Range, Processed Over 16.7ms 2.2V Full-Scale Input Range 6V Overvoltage Protected Inputs Internal Crystal Oscillator 2.5V, 50ppm/C Internal Reference or External Reference Programmable Output Data Rate 0.25ksps to 64ksps Range 0.065% Resolution Programmable Sampling Phase 0 to 333s Delay in 1.33s Steps SPI-/QSPI-/MICROWIRE-/DSP-Compatible 4-Wire Serial Interface Cascadable Interface Allows Control of Up to Eight Devices with a Single CS Signal 3.0V to 3.6V Analog Supply Voltage 2.7V to VAVDD Digital Supply Voltage 38-Pin TSSOP Package
MAX11040
The MAX11040 is a 24-bit, 4-channel, simultaneoussampling, sigma-delta analog-to-digital converter (ADC). The device allows simultaneous sampling of as many as 32 channels using a built-in cascade feature to synchronize as many as eight devices. The serial interface of the MAX11040 allows reading data from all the cascaded devices using a single command. Four modulators simultaneously convert each fully differential analog input with a programmable data output rate ranging from 0.25ksps to 64ksps. The device achieves 106dB SNR at 16ksps and 117dB SNR at 1ksps. The MAX11040 operates from a single +3V supply. The differential analog input range is 2.2V when using the internal reference, an external reference is optional. Each input is overvoltage protected up to 6V without damage. The device uses an internal crystal oscillator or an external source for clock. The MAX11040 is compatible with SPITM, QSPITM, MICROWIRETM, and DSP-compatible 4-wire serial interfaces. An on-board interface logic allows one serial interface (with a single chip select) to control up to eight cascaded devices or 32 simultaneous sampling analog input channels. The MAX11040 is ideally suited for power-management systems. Each channel includes an adjustable sampling phase enabling internal compensation for phase shift due to external dividers, transformers, or filters at the inputs. The output data rate is adjustable with a 0.065% resolution (at 16ksps or below) to track the varying frequency of a periodic input. A SYNC input allows periodic alignment of the conversion timing of multiple devices with a remote timing source. The MAX11040 is available in a 38-pin TSSOP package specified over the -40C to +105C industrial temperature range.
Functional Diagram
OVRFLW FAULT
AIN0+ AIN0REF0 AIN1+ AIN1REF1 AIN2+ AIN2REF2 AIN3+ AIN3REF3
24-BIT ADC
DIGITAL FILTER
SYNC DRDYIN
Applications
Power Protection Relay Equipment Multiphase Power Systems Industrial Data-Acquisition Systems Medical Instrumentation
24-BIT ADC
DIGITAL FILTER
DRDYOUT REGISTERS AND DIGITAL CONTROL SERIAL INTERFACE CASCIN CASCOUT CS SCLK
24-BIT ADC
DIGITAL FILTER
24-BIT ADC
DIGITAL FILTER
DIN DOUT
Ordering Information
MAX11040
PART MAX11040GUU+
TEMP RANGE -40C to +105C
PIN-PACKAGE 38 TSSOP
REFIO 2.5V REFERENCE CRYSTAL OSCILLATOR
+Denotes a lead(Pb)-free/RoHS-compliant package.
AGND
XIN
XOUT
CLKOUT
DGND
MICROWIRE is a trademark of National Semiconductor Corp. SPI/QSPI are trademarks of Motorola Inc.
Pin Configuration appears at end of data sheet.
1
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
MAX11040
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND ........................................................-0.3V to +4V DVDD to DGND ......................................-0.3V to (VAVDD + 0.3V) AGND to DGND.....................................................-0.3V to +0.3V DIN, SCLK, CS, XIN, SYNC, DRDYIN, CASCIN to DGND..............................-0.3V to (VDVDD + 0.3V) DOUT, DRDYOUT, CASCOUT, CLKOUT, XOUT to DGND..................................-0.3V to (VDVDD + 0.3V) FAULT, OVRFLW to DGND ...................................-0.3V to +4.0V AIN_+ to AIN_- ......................................................-6.0V to +6.0V AIN_ _to AGND (VAVDD 3V, VDVDD 2.7V, FAULTDIS = 0, SHDN = 0, fXIN CLOCK 20MHz)....................-6.0V to +6.0V AIN_ _ to AGND (VAVDD < 3V or VDVDD < 2.7V or FAULTDIS = 1 or SHDN = 1 or fXIN CLOCK < 20MHz)........................................-3.5V to +3.5V REFIO, REF_ to AGND............................-0.3V to (VAVDD + 0.3V) Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 38-Pin TSSOP (derated 13.7mW/C above +70C) ...1096mW Operating Temperature Range .........................-40C to +105C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C Soldering Temperature (reflow) .......................................+260C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = +3.0V to +3.6V, VDVDD = +2.7V to VAVDD, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = +2.5V (external), CREFIO = CREF0 = CREF1 = CREF2 = CREF3 = 1F to AGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER DC ACCURACY (Note 2) Resolution Differential Nonlinearity Integral Nonlinearity (Note 3) Offset Error Gain Error Offset-Error Drift Gain-Error Drift Change in Gain Error vs. fOUT Channel-to-Channel Gain Matching DYNAMIC SPECIFICATIONS (62.5Hz sine-wave input, 2.17VP-P) Signal-to-Noise Ratio Total Harmonic Distortion Signal-to-Noise Plus Distortion Spurious-Free Dynamic Range Relative Accuracy (Note 7) Bandwidth Latency Passband Flatness Amplitude-Dependent Phase Error Channel-to-Channel Phase Matching Phase-Error Drift SNR THD SINAD SFDR (Note 6) TA = +25C and +105C TA = -40C TA = +25C and +105C TA = -40C TA = +25C and +105C TA = -40C 0.1% FS input 6.0% FS input -3dB (Note 8) From DC to 1.4kHz FS vs. 0.1% FS 3.4 405 < 0.1 < 0.01 0.0001 0.001 0.12 93 89 94 89 0.25 0.005 100 98 103 106 -94 -90 dB dB dB dB % kHz s dB Deg Deg Deg (Note 4) (Note 5) (Note 5) fOUT = 0.25ksps to 64ksps DNL INL 24-bit no missing code TA = +25C and +105C TA = -40C -1 -1 0.5 1 < 0.025 0.03 24 0.1 0.001 0.004 0.006 +1 +1 Bits LSB % FS mV % FS ppm/C ppm/C % FS % FS SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.0V to +3.6V, VDVDD = +2.7V to VAVDD, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = +2.5V (external), CREFIO = CREF0 = CREF1 = CREF2 = CREF3 = 1F to AGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Channel-to-Channel Isolation Comon-Mode Rejection ANALOG INPUTS (AIN_+, AIN_-) Differential FS Input Range Positive Fault Threshold Negative Fault Threshold Fault Pin Response Time Input Impedance DC Leakage Current Input Sampling Rate Input Sampling Capacitance INTERNAL REFERENCE REFIO Output Voltage REFIO Output Resistance REFIO Temp Drift REFIO Long-Term Stability REFIO Output Noise REFIO Power-Supply Rejection EXTERNAL REFERENCE REFIO Input Voltage REFIO Sink Current REFIO Source Current REFIO Input Capacitance CRYSTAL OSCILLATOR (XIN, XOUT) Tested Resonant Frequency Maximum Crystal ESR Oscillator Startup Time Oscillator Stability Maximum Oscillator Load Capacitance DIGITAL INPUTS (SCLK, CS, DIN, SYNC, CASCIN, DRDYIN, XIN) Input Low Voltage Input High Voltage Input Hysteresis Input Leakage Current Input Capacitance VIL VIH VHYS IL CIN VDVDD = 3.0V 0.7 x VDVDD 100 0.01 15 1 0.3 x VDVDD V V mV A pF VDVDD = 3.3V, excluding crystal (Note 10) 24.576 30 <2 10 10 MHz ms ppm/C pF VREF 2.3 200 200 10 2.7 V A A pF PSRR VREF TA = TMAX 2.4 2.5 1 50 200 3 75 2.6 V k ppm/C ppm/ 1000hr VRMS dB ZIN IIN fS VNFT VIN VPFT VIN < VNFT or VIN > VPFT VAIN_+ = VAIN_fS = fXINCLOCK/8 VIN VPFT VNFT VAIN_+ - VAIN_VAIN_+ or VAIN_- (Note 9) VAIN_+ or VAIN_- (Note 9) -2.2 2.25 -2.65 2.5 130 > 0.5 0.01 3.072 4.0 1 +2.2 2.65 -2.25 V V V s k A Msps pF CMRR SYMBOL CONDITIONS MIN TYP -130 109 MAX UNITS dB dB
MAX11040
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3
24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
MAX11040
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.0V to +3.6V, VDVDD = +2.7V to VAVDD, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = +2.5V (external), CREFIO = CREF0 = CREF1 = CREF2 = CREF3 = 1F to AGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX 0.15 x VDVDD 0.85 x VDVDD 1 15 0.15 x VDVDD 0.85 x VDVDD 30 AVDD DVDD IAVDD IDVDD Normal operation Shutdown and f XINCLOCK = 0Hz Normal operation Shutdown and f XINCLOCK = 0Hz VAVDD = 3.3V + 100mVP-P at 1kHz VAVDD = VDVDD = 3.0V to 3.6V ESD tSCP tPW tSU tHD tDOT tDOE tDOD tCSW tSC tCOT CLOAD = 100pF CLOAD = 30pF CLOAD = 100pF CLOAD = 30pF CLOAD = 30pF 0.3 0.7 16 16 20 Human Body Model 50 20 10 0 1.5 10 < 16 20 16 16 3.0 2.7 25 0.1 11 0.3 70 75 2.5 3.6 VAVDD 35 5 15 UNITS
CMOS DIGITAL OUTPUTS (DOUT, CASCOUT, DRDYOUT, CLKOUT) Output Low Voltage Output High Voltage Three-State Leakage Current Three-State Capacitance VOL VOH ILT COUT I SINK = 5mA I SOURCE = 1mA V V A pF
OPEN-DRAIN DIGITAL OUTPUTS (OVRFLW, FAULT) Output Low Voltage Output High Voltage Internal Pullup Resistance POWER REQUIREMENTS Analog Supply Voltage Digital Supply Voltage Analog Supply Current (Note 11) Digital Supply Current (Note 11) AC Positive-Supply Rejection DC Positive-Supply Rejection ESD PROTECTION All Pins SCLK Clock Period SCLK Pulse Width (High and Low) DIN or CS to SCLK Fall Setup SCLK Fall to DIN or CS Hold SCLK Rise to DOUT Valid CS Fall to DOUT Enable CS Rise to DOUT Disable CS Pulse Width CASCIN to SCLK Rise Setup SCLK Rise to CASCOUT Valid kV ns ns ns ns ns ns ns ns ns ns TIMING CHARACTERISTICS (Figures 7-10) V V mA A mA A dB dB VOL VOH I SINK = 5mA Internal pullup only V V k
4
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24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.0V to +3.6V, VDVDD = +2.7V to VAVDD, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = +2.5V (external), CREFIO = CREF0 = CREF1 = CREF2 = CREF3 = 1F to AGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYNC Pulse Width XIN Clock Pulse Width DRDYIN to DRDYOUT XIN Clock to DRDYOUT Delay XIN Clock Period XIN Clock to SYNC Setup SYNC to XIN Clock Hold XIN to CLKOUT Delay Power-On Reset Delay SYMBOL tSYN tXPW tDRDY tXDRDY tXP tSS tHS tXCD (Note 13) <1 (Note 12) (Note 12) CONDITIONS MIN 2 16 CLOAD = 30pF DRDYIN = DGND 40 16 5 40 20 40 TYP MAX UNITS XIN Clock Cycles ns ns ns ns ns ns ns ms
MAX11040
Note 1: Devices are production tested at +105C. Specifications to -40C are guaranteed by design. Note 2: Tested at VAVDD = VDVDD = +3.0V. Note 3: Integral nonlinearity is the deviation of the analog value at any code from its ideal value after the offset and gain errors are removed. Note 4: Offset nulled. Note 5: Offset and gain drift defined as change in offset and gain error vs. full scale. Note 6: Noise measured with AIN_+ = AIN_- = AGND. Note 7: Relative accuracy is defined as the difference between the actual RMS amplitude and the ideal RMS amplitude of a 62.5Hz sine wave, measured over one cycle at a 16ksps data rate, expressed as a fraction of the ideal RMS amplitude. The relative accuracy specification refers to the maximum error expected over 1 million measurements. Calculated from SNR. Not production tested. Note 8: Latency is a function of the sampling rate and XIN clock. See the Latency section in the Digital Filter section. Note 9: Voltage levels below the positive fault threshold and above the negative fault threshold, relative to AGND on each individual AIN_+ and AIN_- input, do not trigger the analog input protection circuitry. Note 10: Test performed using RXD MP35. Note 11: All digital inputs at DGND or DVDD. Note 12: SYNC is captured by the subsequent XIN clock if this specification is violated. Note 13: Delay from DVDD exceeds 2.0V until digital interface is operational.
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5
24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
MAX11040
Typical Operating Characteristics
(VAVDD = VDVDD = 3.3V, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = 2.5V (external), CREFIO = CREF0 = CREF1 = CREF2 = CREF3 = 1F, TA = +25C, unless otherwise noted.)
INL vs. DIFFERENTIAL INPUT VOLTAGE
MAX11040 toc01
HISTOGRAM OF RMS AMPLITUDE AT 0.1% FS
MAX11040 toc02
MAXIMUM EXPECTED ERROR OF CALCULATED RMS AMPLITUDE vs. INPUT AMPLITUDE
1 MILLION 62.5Hz CYCLES MAXIMUM EXPECTED ERROR (%)
MAX11040 toc03
0.005 0.004 0.003 0.002 INL (% FS) 0.001 0 -0.001 -0.002 -0.003 -0.004 -0.005 -2.5 -1.5 -0.5 0.5 1.5
500 450 400 350 INSTANCES 300 250 200 150 100 50 0.09970 0.09976 0.09982 0.09988 0.09994 0.10000 0.10006 0.10012 0.10018 0.10024
1
0.1
0.01
2.5
0.10030
0 DIFFERENTIAL INPUT VOLTAGE (V)
0.001 0.01 0.1 1 10 100 INPUT AMPLITUDE (% FS)
RMS AMPLITUDE (% FS)
SIGNAL-TO-NOISE RATIO vs. OUTPUT DATA RATE
MAX11040 toc04
FFT vs. FREQUENCY AT FULL SCALE
MAX11040 toc05
FFT vs. FREQUENCY AT 0.1% FULL SCALE
60Hz SINE-WAVE INPUT -60 AMPLITUDE (dB FS) -80 -100 -120 -140 -160 -180
MAX11040 toc06
130
0 60Hz SINE-WAVE INPUT -20 AMPLITUDE (dB FS) -40 -60 -80 -100
-40
120
SNR (dB)
110
100
90
-120 -140 0.1 1 10 100 0 1000 2000 3000 4000 5000 6000 7000 8000 FREQUENCY (Hz) OUTPUT DATA RATE (ksps)
80
0
1000 2000 3000 4000 5000 6000 7000 8000 FREQUENCY (Hz)
RMS AMPLITUDE vs. INPUT FREQUENCY
MAX11040 toc07
RMS AMPLITUDE GAIN ERROR vs. OUTPUT DATA RATE
MAX11040 toc08
RMS AMPLITUDE vs. SOURCE RESISTANCE
0 -1 RMS AMPLITUDE (dB) -2 -3 -4 -5 -6 -7 -8 -9
MAX11040 toc09
0.1 0 RMS AMPLITUDE (dB) -0.1 -0.2 -0.3 -0.4 -0.5 10 100 1000
0.05 0.04 RMS AMPLITUDE GAIN ERROR (%) 0.03 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05
1
10,000
100
1000
10,000
100,000
10
100
1000
10,000
100,000
INPUT FREQUENCY (Hz)
OUTPUT DATA RATE (Hz)
SOURCE RESISTANCE ()
6
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24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = 3.3V, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = 2.5V (external), CREFIO = CREF0 = CREF1 = CREF2 = CREF3 = 1F, TA = +25C, unless otherwise noted.)
TOTAL HARMONIC DISTORTION vs. INPUT FREQUENCY
MAX11040 toc10
MAX11040
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX11040 toc11
OFFSET ERROR vs. TEMPERATURE
0.08 0.06 OFFSET ERROR (% FSR) 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 AVDD = DVDD
MAX11040 toc12
-80
0.10 0.08 0.06 OFFSET ERROR (% FSR) 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 AVDD = DVDD
0.10
-90
THD (dB)
-100
-110
-120
-130 0 500 1000 1500 2000 INPUT FREQUENCY (Hz)
-0.10 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
-40
-11
18
47
76
105
TEMPERATURE (C)
GAIN ERROR vs. SUPPLY VOLTAGE
MAX11040 toc13
GAIN ERROR vs. TEMPERATURE
0.8 0.6 GAIN ERROR (% FSR) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -0.10 -40 -15 10 35 60 85 -0.08 AVDD = DVDD = 3.3V
MAX11040 toc14
GAIN ERROR DRIFT
MAX11040 toc15
1.0 0.8 0.6 GAIN ERROR (% FSR) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 3.0 3.1 3.2 3.3 3.4 3.5 AVDD = DVDD
1.0
0
-0.02 GAIN ERROR (%)
-0.04
-0.06
3.6
0 100 200 300 400 500 600 700 800 900 1000 TIME (h)
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX11040 toc16
SUPPLY CURRENT vs. TEMPERATURE
MAX11040 toc17
SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
AVDD = DVDD 400 SUPPLY CURRENT (nA)
MAX11040 toc18
30 AVDD = DVDD 25 SUPPLY CURRENT (mA) 20 15 10 5 0 3.0 3.1 3.2 3.3 3.4 3.5
30 25 SUPPLY CURRENT (mA) 20 15 10 5 0
AVDD = DVDD = 3.3V
500
IAVDD IDVDD
IAVDD
300
200
IDVDD
IDVDD
100 IAVDD 0 -40 -11 18 47 76 105 3.0 3.1 3.2 3.3 3.4 3.5 3.6 TEMPERATURE (C) SUPPLY VOLTAGE (V)
3.6
SUPPLY VOLTAGE (V)
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7
24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
MAX11040
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = 3.3V, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = 2.5V (external), CREFIO = CREF0 = CREF1 = CREF2 = CREF3 = 1F, TA = +25C, unless otherwise noted.)
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
AVDD = DVDD = 3.6V
MAX11040 toc19
CRYSTAL OSCILLATOR STARTUP TIME
MAX11040 toc20
1000
800 SUPPLY CURRENT (nA)
600 IAVDD 400 IDVDD 200
CLKOUT 500mV/div
0 -40 -11 18 47 76 105 40s/div TEMPERATURE (C)
Pin Description
PIN 1 2 3 4, 8, 10, 29, 31, 35 5 6 7 9 11, 28 12, 27 NAME AIN0AIN0+ REF0 AGND AIN1AIN1+ REF1 REFIO DGND DVDD Negative Analog Input Channel 0 Positive Analog Input Channel 0 ADC0 Buffered Reference Voltage. Bypass REF0 with a 1F capacitor to AGND. Analog Ground Negative Analog Input Channel 1 Positive Analog Input Channel 1 ADC1 Buffered Reference Voltage. Bypass REF1 with a 1F capacitor to AGND. Reference Voltage Output/Input. Reference voltage for analog-to-digital conversion. In internal reference mode, the reference buffer provides a +2.5V nominal output. In external reference mode, overdrive REFIO with an external reference between 2.3V to 2.7V. Bypass REFIO with a 1F capacitor to AGND. Digital Ground Positive Digital Supply Voltage. Bypass each DVDD to DGND with a 1F capacitor in parallel with a 0.01F capacitor as close as possible to the device. Cascade Input. A logic-low on CASCIN while CS is a logic-low during the last cycle of a byte signals the device to perform the requested data transfer during subsequent bytes using DIN and DOUT. Once the requested transfer is completed, the part three-states DOUT and ignores DIN until a new command is issued. CASCIN is clocked in at the rising edge of SCLK. Connect CASCIN to DGND when not daisy chaining multiple devices. See the Multiple Device Connection section for connection recommendations. FUNCTION
13
CASCIN
14
Cascade Output. CASCOUT is driven low during the last cycle of the last byte of a data transfer to signal the next device in the daisy chain to begin transferring data on the next byte. CASCOUT changes after the CASCOUT rising edge of SCLK. Leave CASCOUT unconnected when not daisy chaining multiple devices. See the Multiple Device Connection section. CS Active-Low Chip-Select Input. A falling edge on CS while CASCIN is a logic-low enables DIN and DOUT for data transfer. A logic-high on CS prevents data from being clocked in on DIN and places DOUT in a high-impedance state.
15
8
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24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
Pin Description (continued)
PIN 16 17 NAME SCLK DIN FUNCTION Serial-Clock Input. Clocks in data at DIN on the falling edge of SCLK and clocks out data at DOUT on the rising edge of SCLK. Serial Data Input. Data at DIN is clocked in on the falling edge of SCLK. Serial Data Output. The drive for DOUT is enabled by a falling edge on CS while CASCIN is low or by a falling edge on CASCIN while CS is low. DOUT is disabled/three-stated when CS is high or after the appropriate number of data bytes have been transferred in response to the requested command. Data is clocked out at DOUT on the rising edge of SCLK. Active-Low Overvoltage Fault Indicator Output. FAULT goes low when any analog input goes outside the fault threshold range (between VPFT and VNFT). The FAULT output is open drain with a 30k internal pullup resistor, allowing wire-NOR functionality. See the Analog Input Overvoltage and Fault Protection section. Active-Low Channel Data Overflow Output. OVRFLW goes low when a conversion result goes outside the voltage range bounded by the positive and negative full scale on one or more of the analog input channels or when FAULT goes low. The OVRFLW output is open drain with a 30k internal pullup resistor, allowing wire-NOR functionality. See the Analog Input Overvoltage and Fault Protection section. Buffered Clock Output. When the XTALEN bit in the configuration register is 1 and a crystal is installed between XIN and XOUT, CLKOUT provides a buffered version of the internal oscillator's clock. Setting the XTALEN bit to 0 places CLKOUT in a high-impedance state.
MAX11040
18
DOUT
19
FAULT
20
OVRFLW
21
CLKOUT
22
Active-Low Data Ready Output. When DRDYIN = 0, DRDYOUT outputs a logic-low to indicate the DRDYOUT availability of a new conversion result. DRDYOUT transitions high at the next CS falling edge or when DRDYIN = 1. See the Multiple Device Connection section. DRDYIN Active-Low Data Ready Input. A logic-high at DRDYIN causes DRDYOUT to output a logic-high. When DRDYIN = 0, DRDYOUT outputs a logic-low when a new conversion result is available. See the Multiple Device Connection section. Connect DRDYIN to DGND when not daisy chaining multiple devices. Sampling Synchronization Input. The falling edge of SYNC aligns sampling and output data so that multiple devices sample simultaneously. Synchronize multiple devices running from independent crystals by connecting DRDYOUT of the last device in the chain to the SYNC inputs of all devices in the chain. Connect SYNC to DGND for single device operation. See the Multiple Device Connection section. Crystal Oscillator Output. Connect a 24.576MHz external crystal or resonator between XIN and XOUT when using the internal oscillator. Leave XOUT unconnected when driving the MAX11040 with an external frequency. See the Crystal Oscillator section. Crystal Oscillator/Clock Input. Connect a 24.576MHz external crystal or resonator between XIN and XOUT when using the internal oscillator or drive XIN with an external clock and leave XOUT unconnected. See the Crystal Oscillator section. Positive Analog Supply Voltage. Bypass to AGND with a 1F capacitor in parallel with a 0.01F capacitor as close as possible to the device. ADC3 Buffered Reference Voltage. Bypass with a 1F capacitor to AGND. Positive Analog Input Channel 3 Negative Analog Input Channel 3 ADC2 Buffered Reference Voltage. Bypass with a 1F capacitor to AGND. Positive Analog Input Channel 2 Negative Analog Input Channel 2
23
24
SYNC
25
XOUT
26
XIN
30 32 33 34 36 37 38
AVDD REF3 AIN3+ AIN3REF2 AIN2+ AIN2-
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9
24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
MAX11040
Typical Operating Circuit
1F 3.3V 3.3V 1F
the effective sample rate of the ADC, is software programmable. The MAX11040 operates from a single 3.0V to 3.6V analog supply and a 2.7V to VAVDD digital supply. The 4-wire serial interface is SPI/QSPI/MICROWIRE and DSP compatible.
0.01F AVDD AIN0+ AIN01F AIN0+ AIN0REF0 DVDD
0.01F 20pF XIN 24.576MHz XOUT 20pF
ADC Modulator
Each channel of the MAX11040 performs analog-todigital conversion on its input using a dedicated switched-capacitor sigma-delta modulator. The modulator converts the input signal into low-resolution digital data for which the average value represents the digitized signal information at 3.072Msps for a 24.576MHz XIN clock. This data stream is then presented to the digital filter for processing to remove the high-frequency noise that creates a high-resolution 24-bit output data stream. The input sampling network of the analog input consists of a pair of 4pF capacitors (C SAMPLE ), the bottom plates of which are connected to AIN_+ and AIN_- during the track phase and then shorted together during the hold phase (see Figure 1). The internal switches have a total series resistance of 400. Given a 24.576MHz XIN clock, the switching frequency is 3.072MHz. The sampling phase lasts for 120ns.
MAX11040
AIN1+ AIN11F AIN1+ AIN1REF1
CLKOUT CASCOUT CASCIN
AIN2+ AIN21F
AIN2+ AIN2REF2
OVRFLW FAULT
CS AIN3+ AIN31F AIN3+ AIN3REF3 SCLK DIN DOUT SYNC DRDYOUT REFIO 1F AGND DRDYIN DGND MICROCONTROLLER OR DSP
MAX11040
TRACK AIN_+ CSAMPLE+
Detailed Description
The MAX11040 is a 24-bit, simultaneous-sampling, 4-channel, sigma-delta ADC including support for synchronized sampling and daisy chaining of the serial interface across multiple (up to eight) MAX11040 devices. The serial interface of the set of synchronized devices behaves as one device. Each channel includes a differential analog input, a sigma-delta modulator, a digital decimation filter, an independent programmable sampling delay, and a buffered reference signal from the internal or an external reference. The device contains an internal crystal oscillator. The output data rate,
HOLD CSAMPLETO ADC AIN_TRACK RON RON
AVDD/2
Figure 1. Simplified Track/Hold Stage
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24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
Digital Filter
The MAX11040 contains an on-chip digital lowpass filter that processes the data stream from each modulator and generates the high-resolution output data. The lowpass filter frequency response is determined by the programmable output data rate. At the nominal 16ksps output data rate, the -3dB bandwidth of the filter is 3.4kHz. The passband flatness is better than 0.1dB from 0 to 1.74kHz. The notches are located at 5.75kHz and 7.195kHz. These frequencies scale linearly with the output data rate. See Figure 2 and Table 1 for the frequency response at different data rates. Since the transfer function of a digital filter is repeatable and predictable, it is possible to correct for frequencydependent attenuation in downstream software. See the Compensating for the Rolloff of the Digital Filter in a Typical FFT Analysis section. The transfer function is defined by the following equation: fAIN fSAMPLE x sin x f SAMPLE Gain(fAIN ) = fAIN fXINCLOCK x sin x fXINCLOCK where: Gain is the filter gain. fAIN is the analog input frequency. fSAMPLE is the programmed output data rate, nominally 16kHz. fXINCLOCK is the clock frequency at XIN, nominally 24.576MHz. FIR_Gain (fAIN) is the normalized gain of the FIR filter with the following filter coefficients, as a function of the analog input frequency fAIN. These coefficients are applied at the output data rate: + 0.021484375 - 0.072265625 - 0.035156250 + 0.304687500 + 0.539062500 + 0.304687500 - 0.035156250 - 0.072265625 + 0.021484375
3
MAX11040
0 -1 GAIN (dB) -2 -3 -4 -5 -6 0 0.4 0.8 0.12 0.16 0.20 0.24
0.28
fAIN/fSAMPLE
Figure 2. Digital Filter Response
Table 1. Bandwidth vs. Output Data Rate
OUTPUT DATA RATE (ksps) 0.5 1 2 4 8 10 12 16 32 64 -3dB BANDWIDTH (kHz) 0.11 0.21 0.42 0.85 1.69 2.11 2.54 3.38 6.78 13.5 -0.1dB BANDWIDTH (kHz) 0.05 0.11 0.22 0.43 0.87 1.09 1.31 1.74 3.48 6.96
MAX11040 fig02
1
Latency The digital filter determines the latency of the MAX11040. Latency is defined as the time between the effective point in time that a sample is taken and when the resulting digital data is available for reading.
The latency of the converter is specified by the following equation: Latency = (6 x tDOUT) + (PHI x 1.3s) + 30s where tDOUT is the data output period (inverse of the programmed sample rate), determined by fXINCLOCK and the selected output data rate, and PHI is the programmed sampling instant delay for the channel in question (0 PHI 255). The latency is approximately 405s at 16ksps.
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24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
MAX11040
Modulator Clock
The modulator clock is created by dividing the frequency at the XIN input by a factor of 8. The XIN input is driven either directly by an external clock or by the on-chip crystal oscillator.
Analog Input Overvoltage and Fault Protection
The full-scale differential input range of the MAX11040 is 0.88VREF. The converter accurately represents any input for which the positive and negative analog inputs are separated by a magnitude of less than 0.88VREF. The device includes special circuitry that protects it against voltages on the analog inputs up to +6V. Setting FAULTDIS = 1 disables the protection circuitry. There are two mechanisms of overvoltage detection and protection: full-scale overflow and overvoltage fault. Full-scale overflow occurs if the magnitude of the applied input voltage on any one or more channels is greater than 0.88VREF. In this case, the digital output is clipped to positive or negative full scale and the OVRFLW flag goes low. Overvoltage fault occurs if the magnitude of an applied input voltage on any one or more channels goes outside the fault-detection thresholds. The reaction to an overvoltage fault is dependent on whether the fault-protection circuitry is enabled. If enabled, the input-protection circuits engage and the FAULT flag goes low. A full-scale overflow or an overvoltage fault condition on any one channel does not affect the output data for the other channels. The input protection circuits allow up to 6V relative to AGND on each input, and up to 6V differentially between AIN+ and AIN-, without damaging the device only if the following conditions are satisfied: power is applied, the device is not in shutdown mode, a clock frequency of at least 20MHz is available at XIN, and FAULTDIS = 0. The analog inputs allow up to 3.5V relative to AGND when either the MAX11040 is placed in shutdown mode, the clock stops, or FAULTDIS = 1. During an overvoltage fault condition the impedance between AIN_+ and AIN_- reduces to as low as 0.5k. The output structure and cascading features of FAULT and OVRFLW are discussed in the Multiple Device Digital Interface section.
Crystal Oscillator The on-chip oscillator requires an external crystal (or resonator) with a 24.576MHz operating frequency connected between XIN and XOUT, as shown in Figure 3. As in any crystal-based oscillator circuit, the oscillator frequency is sensitive to the capacitive load (CL). CL is the capacitance that the crystal needs from the oscillator circuit and not the capacitance of the crystal. The input capacitance across XIN and XOUT is 1.5pF.
Choose a crystal with a 24.576MHz oscillation frequency and an ESR less than 30, such as the MP35 from RXD Technologies. See Figure 3 for the block diagram of the crystal oscillator. Set XTALEN = 1 in the configuration register to enable the crystal oscillator. The CLKOUT output provides a buffered version of the clock that is capable of driving eight MAX11040 devices, allowing synchronized operation from a single crystal. See the Multiple Device Synchronization section in the Applications Information section.
External Clock To use an external clock, set XTALEN = 0 in the Configuration register and connect an external clock source (20MHz-25MHz) to XIN. CLKOUT becomes high impedance.
MAX11040
20pF XIN 24.576MHz OSCILLATOR XOUT
24.576MHz
20pF
Analog Input Overflow Detection and Recovery (OVRFLW) The OVRFLW flag is set based on the ADC conversion result. When the applied voltage on one or more analog inputs goes outside the positive or negative full scale (0.88VREF), OVRFLW asserts after a delay defined by the latency of the converter, coincident with the DRDYOUT of the full-scale clamped conversion result (see Figure 4). The specifics of the latency are discussed earlier in the data sheet in the Latency section.
Figure 3. Crystal Oscillator Input
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24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
When the analog input voltage changes between the ADC full scale and the fault threshold faster than the latency of the converter, OVRFLW goes low with the FAULT output. OVRFLW remains invalid until a valid clock frequency is available at XIN. the latency of the converter, the ADC conversion result prematurely jumps to the full-scale value when a fault is detected (see Detection Discontinuity in Figure 4). During a fault condition and the subsequent faultrecovery time, the ADC conversion result remains at full scale. This creates a discontinuity in the digital conversion result only if the fault recovery time is greater than the latency plus the time that the input changes between the fault threshold and the ADC full scale (see Recovery Discontinuity in Figure 4). Neither of these steps occur if the fault-protection circuitry is disabled (FAULTDIS = 1), or if the input is slow relative to the above descriptions (see Figure 5). For data rates faster than 32ksps (FSAMPC = 111), the converter output may contain invalid data for up to 188s after FAULT returns high. To prevent this behavior, disable the overvoltage fault protection by setting the FAULTDIS bit in the configuration register to 1 when using FSAMPC = 111, and limit the analog input swing to 3.5V.
MAX11040
Overvoltage Fault Detection and Recovery (FAULT) With overvoltage fault protection enabled (FAULTDIS = 0), FAULT immediately transitions from a high to low when any of the analog inputs go outside the voltage range bounded by the fault-detection thresholds VPFT and VNFT. Once the analog inputs return back within the fault thresholds, the FAULT interrupt output goes high after a delay called the fault-recovery time. The fault-recovery time is: 20 x tDOUT < fault-recovery time < 25 x tDOUT where tDOUT is the data output period determined by fXINCLOCK and the selected output data rate. In the event the analog input voltage changes between the ADC full scale and the fault threshold faster than
|AIN+ - AIN-| DETECTION DISCONTINUITY RECOVERY DISCONTINUITY
FAULT-DETECTION THRESHOLD (VPFT OR |VNFT|)
FULL SCALE (|0.88VREF|) LATENCY DIGITAL OUTPUT DATA AT DOUT LATENCY LATENCY RECOVERY TIME
LATENCY
FAULT
OVRFLW
Figure 4. High-Frequency Analog Input Overvoltage Detection and Recovery
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24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
MAX11040
|AIN+ - AIN-|
FAULT DETECTION THRESHOLD (VPFT OR |VNFT|)
LATENCY
LATENCY
FULL SCALE (|0.88VREF|)
LATENCY
RECOVERY TIME DIGITAL OUTPUT DATA AT DOUT LATENCY
FAULT
OVRFLW
Figure 5. Low-Frequency Analog Input Overvoltage Detection and Recovery
Reference
The MAX11040 operates with either a +2.5V internal bandgap reference or an external reference source between +2.3V and +2.7V applied at REFIO. Bypass REFIO and each REF_ to AGND with a 1F capacitor. The reference voltage sets the positive and negative full-scale voltage according to the following formula: FS = 0.88 VREFIO The reference voltage at REFIO (external or internal) is individually buffered to generate the reference voltages at REF0 to REF3 (see Figure 6.) These independent buffers minimize the potential for crosstalk between each of the internal ADCs.
REF0 REF1 REF2 REF3
REFIO
+2.5V REFERENCE
Serial Interface
The MAX11040 interface is fully compatible with SPI/DSP standard serial interfaces (compatible with SPI modes CPOL = 0, CPHA = 0 and CPOL = 1, and CPHA = 1). The serial interface provides access to four onchip registers: Sampling Instant Control register (32 bits), Data Rate Control register (16 bits), Configuration register (8 bits), and Data register (96 bits). All serialinterface commands begin with a command byte, which addresses a specific register, followed by data bytes with a data length that depends on the specific
Figure 6. REFIO Input
register addressed and the number of devices cascaded (see Figures 7, 8, and the Registers section). The serial interface consists of eight signals: CS, SCLK, DIN, DOUT, CASCIN, CASCOUT, DRDYIN, and DRDYOUT. CASCIN, CASCOUT, DRDYIN, and DRDYOUT are used for daisy chaining multiple devices together. See the Multiple Device Connection section for details on how to connect CASCIN, CASCOUT,
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24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
DRDYIN, and DRDYOUT. For single-device applications, connect CASCIN and DRDYIN to DGND and drive CS low to transfer data in and out of the MAX11040. With DRDYIN low, a falling edge at the data ready signal output (DRDYOUT) indicates that new conversion results are available for reading in the 96-bit data register. A falling edge on SCLK clocks in data at DIN. Data at DOUT changes on the rising edge of SCLK and is valid on the falling edge of SCLK. DIN and DOUT are transferred MSB first. Drive CS high to disable the interface and place DOUT in a high-impedance state. An interface operation with the MAX11040 takes effect on the last rising edge of SCLK. If CS goes high before the complete transfer, the write is ignored. Every data transfer is initiated by the command byte. The command byte consists of an R/W bit and 7 address bits (see Table 2.) Figures 7 and 8 show the timing for read and write operations, respectively.
MAX11040
tCSW tSU CS tPW tDOD SCLK tSU DIN R/W A6 A5 A4 A3 A2 A1 A0 tHD DOUT HIGH-Z tDOE DATA LENGTH (NUMBER OF BYTES) DEPENDS ON THE REGISTER BEING READ (SEE TABLE 2) DRDYIN tDRDY DRDYOUT DATA READY COMMAND ADDRESS B7 B6 B5 B4 B3 B2 B1 B0 tDOT HIGH-Z tHD tPW tSCP
Figure 7. General Read-Operation Timing Diagram
tCSW tSU CS COMMAND ADDRESS DIN R/W A6 A5 A4 A3 A2 A1 A0 tHD SCLK tPW tPW HIGH-Z tSU tSCP DATA LENGTH (NUMBER OF BYTES) DEPENDS ON THE REGISTER BEING WRITTEN (SEE TABLE 2) B7 B6 B5 B4 B3 B2 B1 B0 tHD
DOUT
HIGH-Z
Figure 8. General Write-Operation Timing Diagram
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24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
MAX11040
Registers
The MAX11040 includes four registers accessible by 7 command bytes. The command bytes provide read and write access to the Data Rate Control register, the Sampling Instant Control register, and the Configuration register and read access to the Data register. See Table 2. Figure 9 shows the CASCIN and CASOUT timing diagram. Figure 10 is the XIN clock, CLKOUT, SYNC, and DRDYOUT timing diagram.
SCLK tCOT CASCOUT (DEVICE n) CASCIN (DEVICE n+1) tSC
Table 2. Command Bytes
R/W 0 1 0
tXP tXPW
ADDRESS [A6:A0] 1000000 1000000 1010000 1010000 1100000 1100000 1110000
DATA LENGTH* 32 x n** bits 32 x n bits 16 bits 16 bits 8 x n bits 8 x n bits 96 x n bits
FUNCTION Write Sampling Instant Control Register Read Sampling Instant Control Register Write Data Rate Control Register Read Data Rate Control Register Write Configuration Register Read Configuration Register Read Data Register
Figure 9. CASCIN and CASCOUT Timing Diagram
XIN CLOCK tXCD CLKOUT tHS tSS SYNC tSYN DRDYOUT tXDRDY
1 0 1 1
*All data lengths are proportional to the number of cascaded devices except for reads and writes to the Data Rate Control register. When accessing the Data Rate Control register, the data length is fixed at 16 bits. These 16 bits are automatically written to all cascaded devices. **n is the total number of cascaded devices.
Figure 10. XIN Clock, CLKOUT, SYNC, and DRDYOUT Timing Diagram
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24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
Sampling Instant Control Register By default, the MAX11040 samples all 4 input channels simultaneously. To delay the sampling instant on one or more channels, program the appropriate byte in the Sampling Instant Control register. The delay of the actual sampling instant of each individual channel from the default sampling instant (PHI_[7:0] = 0x00) is adjustable between 32 to 819,121 XIN clock cycles,
which is 1.3s to 333s with fXINCLOCK at 24.576MHz (see Table 3.)
MAX11040
Configuration Register The Configuration register contains 5 bits that control the functionality of the MAX11040. The default state is 0x00.
The data length of the Configuration register is 8 bits per cascaded device (see Table 4).
Table 3. Sampling Instant Control Register
BIT [31:24] [23:16] [15:8] [7:0] NAME DESCRIPTION Channel 0 sample instant adjust. PHI0 delays sampling instant on channel 0 by 32 XIN clock cycles per PHI0[7:0] LSB, up to 8192 cycles total (1.3s resolution; 333s range at XIN of 24.576MHz). PHI1[7:0] PHI2[7:0] PHI3[7:0] Channel 1 sample instant adjust. PHI1 delays sampling instant on channel 1 by 32 XIN clock cycles per LSB, up to 8192 cycles total (1.3s resolution; 333s range at XIN of 24.576MHz). Channel 2 sample instant adjust. PHI2 delays sampling instant on channel 2 by 32 XIN clock cycles per LSB, up to 8192 cycles total (1.3s resolution; 333s range at XIN of 24.576MHz). Channel 3 sample instant adjust. PHI3 delays sampling instant on channel 3 by 32 XIN clock cycles per LSB, up to 8192 cycles total (1.3s resolution; 333s range at XIN of 24.576MHz).
Table 4. Configuration Register
BIT 7 6 NAME SHDN RST DESCRIPTION Shutdown bit. Set SHDN high to place the device in shutdown mode. In shutdown mode, the internal oscillator, fault circuitry, and internal bandgap reference are turned off. Set SHDN low for normal operation. Reset bit. Set RST high to reset all registers to the default states except for the RST bit, and realign sampling clocks and output data. Enable 24-bit resolution bit. Set EN24BIT high to enable the 24-bit data output. Set EN24BIT low to enable 19-bit data output with device address and channel address tags. Tables 5 and 6 specify the Data register for both states of this bit. Internal oscillator enable bit. When using the on-chip crystal oscillator as the clock source, set XTALEN high to enable the crystal oscillator and provide a buffered version of the crystal clock at the CLKOUT output. When using an external clock source, set XTALEN low to disable the internal crystal oscillator and tri-state the CLKOUT output. Connect the external clock source to the XIN input.
5
EN24BIT
4
XTALEN
3
Overvoltage fault-protection disable bit. Set FAULTDIS high to disable the overvoltage fault-protection circuits. For FAULTDIS = 0, the absolute maximum input range is 6V. Analog inputs beyond the faultdetection threshold range trip the fault-protection circuits. The output remains clipped for a fault-recovery FAULTDIS time (typically < 1.57ms) after the inputs return within the fault-detection threshold range. For FAULTDIS = 1, the absolute maximum input range is only 3.5V, but there is no fault-recovery delay. See the Overvoltage Fault Detection and Recovery section. Don't Care Don't-care bits.
[2:0]
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24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
MAX11040
Data Register The Data register contains the results of the ADC conversion. The result is reported in two's complement format. The register contains one or two pieces of information, depending on the state of EN24BIT in the Configuration register. When EN24BIT is set to zero, the Data register contains the ADC data truncated to 19 bits, followed by the device and channel addresses
(see Table 5). When EN24BIT is set to one, the data contained in the Data register represents the 24-bit conversion (see Table 6). The data length of the Data register is 96 bits for each cascaded device. Figure 11 shows the sequence of the conversion result output of all channels for two cascaded devices. If the results are not read back prior to completion of the next conversion, the data is overwritten.
Table 5. Data Register (EN24BIT = 0)
BIT [95:77] [76:74] [73:72] [71:53] [52:50] [49:48] [47:29] [28:26] [25:24] [23:5] [4:2] [1:0] NAME CH0DATA[18:0] IC[2:0] 00 CH1DATA[18:0] IC[2:0] 01 CH2DATA[18:0] IC[2:0] 10 CH3DATA[18:0] IC[2:0] 11 DESCRIPTION Channel 0 19-bit conversion result (two's complement) Device address tag. IC[2:0] starts with 000 for the device nearest the master. Channel 0 address tag = 00 Channel 1 19-bit conversion result (two's complement) Device address tag. IC[2:0] starts with 000 for the device nearest the master. Channel 1 address tag = 01 Channel 2 19-bit conversion result (two's complement) Device address tag. IC[2:0] starts with 000 for the device nearest the master. Channel 2 address tag = 10 Channel 3 19-bit conversion result (two's complement) Device address tag. IC[2:0] starts with 000 for the device nearests the master. Channel 3 address tag = 11
Table 6. Data Register (EN24BIT = 1)
BIT [95:72] [71:48] [47:24] [23:0] NAME CH0DATA[23:0] CH1DATA[23:0] CH2DATA[23:0] CH3DATA[23:0] DESCRIPTION Channel 0 24-bit conversion result (two's complement) Channel 1 24-bit conversion result (two's complement) Channel 2 24-bit conversion result (two's complement) Channel 3 24-bit conversion result (two's complement)
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24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
MAX11040
CS
DIN SCLK 24 CYCLES CHANNEL 0, DEVICE 0 24 CYCLES CHANNEL 1, DEVICE 0 24 CYCLES CHANNEL 2, DEVICE 0 24 CYCLES CHANNEL 3, DEVICE 0 24 CYCLES CHANNEL 0, DEVICE 1 24 CYCLES CHANNEL 1, DEVICE 1 24 CYCLES CHANNEL 2, DEVICE 1 24 CYCLES CHANNEL 3, DEVICE 1
DOUT CASCOUT0 (CASCIN0 = 0)
DEVICE 1 TAKES OVER SPI BUS
CASCOUT1
DRDYOUT0 (DRDYIN0 = 0)
DEVICE 0 DATA READY
DRDYOUT1
DEVICE 0 AND DEVICE 1 DATA READY
Figure 11. 192-Bit Data Read Operation Diagram for Two Cascaded Devices
Data Rate Control Register The Data Rate Control register controls the output data period, which corresponds to the output data rate of the ADC. The data period is controlled by both a coarse (FSAMPC[2:0]) and a fine (FSAMPF[10:0]) adjustment (see Table 7). The final data rate is derived by dividing the XIN clock frequency by a divider value. The divider value is a function of FSAMPC[2:0] and FSAMPF[10:0]:
Data Rate = fXINCLOCK/Divider Divider = Coarse Cycle Factor x 384 + Fine Cycle Factor x FSAMPF[10:0]
Note: Fractional results for the divider are rounded down to the nearest integer. Coarse cycle factor and fine cycle factor come from Table 7. The effect of FSAMPF[10:0] in the formula has limitations as noted in the table. Examples of output data rate vs. FSAMPC[2:0] and FSAMPF[10:0] are shown in Table 8. Table 9 shows typical device performance for various data rate settings. The data length of the Data Rate Control register is 16 bits total for writes and reads (see Table 2). Changes to the Data Rate Control register take effect within one conversion period.
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24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
MAX11040
Table 7. Data Rate Control Register
BITS NAME Coarse Cycle Factor 4 128 64 32 16 8 2 1 DESCRIPTION Output data rate coarse adjust bits. FSAMPC[2:0] sets the coarse cycle factor. FSAMPC 000 001 [15:13] FSAMPC[2:0] 010 011 100 101 110 111 [12:11] Don't Care Don't-care bits. Output data rate fine adjust bits. FSAMPF[10:0] increases the output data period by a number of XIN clock cycles. This number is the value of the register times the fine cycle factor. Values of FSAMPF greater than 1535 have no additional effect. FSAMPC 000 [10:0] FSAMPF[10:0] 001 010 011 100 101 110 111 XIN Fine Cycle Factor 1 cycle 32 cycles 16 cycles 8 cycles 4 cycles 2 cycles 1/2 cycle 1/4 cycle Sample Rate in ksps (fXIN CLOCK = 24.576MHz) 16 0.5 1 2 4 8 32 64
Table 8. Examples of Output Data Rate as a Function of FSAMPC[2:0] and FSAMPF[10:0]
FSAMPC[2:0] FSAMPF[10:0] 11xxxxxxxxx 001 10111111111 00000000001 00000000000 11xxxxxxxxx 010 10111111111 00000000001 00000000000 11xxxxxxxxx 011 10111111111 00000000001 00000000000 OUTPUT DATA RATE (sps) 250.1 250.1 499.7 500.0 500.2 500.2 999.3 1000.0 1000.3 1000.3 1998.7 2000.0 OUTPUT DATA PERIOD (24.576MHz CLOCK CYCLES) 98272 98272 49184 49152 49136 49136 24592 24576 24568 24568 12296 12288 8 16 32 FSAMPF OUTPUT DATA PERIOD RESOLUTION (24.576MHz CLOCK CYCLES)
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24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
Table 8. Examples of Output Data Rate as a Function of FSAMPC[2:0] and FSAMPF[10:0] (continued)
FSAMPC[2:0] FSAMPF[10:0] 11xxxxxxxxx 100 10111111111 00000000001 00000000000 11xxxxxxxxx 101 10111111111 00000000001 00000000000 11xxxxxxxxx 000 10111111111 00000000001 00000000000 11xxxxxxxxx 110 1011111111x 0000000001x 0000000000x 11xxxxxxxxx 111 101111111xx 000000001xx 000000000xx OUTPUT DATA RATE (sps) 2000.7 2000.7 3997.4 4000.0 4001.3 4001.3 7994.8 8000.0 8002.6 8002.6 15990 16000 16010 16010 31958 32000 32042 32042 63834 64000 OUTPUT DATA PERIOD (24.576MHz CLOCK CYCLES) 12284 12284 6148 6144 6142 6142 3074 3072 3071 3071 1537 1536 1535 1535 769 768 767 767 385 384 1 1 1 2 4 FSAMPF OUTPUT DATA PERIOD RESOLUTION (24.576MHz CLOCK CYCLES)
MAX11040
Table 9. Typical Performance vs. Output Data Rate
OUTPUT DATA RATE (ksps) 0.5 1 2 4 8 10 12 16 32 64 -3dB -0.1dB BANDWIDTH BANDWIDTH (kHz) (kHz) 0.11 0.21 0.42 0.85 1.69 2.11 2.54 3.38 6.78 13.5 0.05 0.11 0.22 0.43 0.87 1.09 1.31 1.74 3.48 6.96 FAULT LATENCY SNR OF 24-BIT RECOVERY (s) DATA (dB) TIME (s) 12030 6030 3030 1530 780 630 530 405 218 124 16375 8375 4375 2375 1375 1175 1042 875 625 500 117 115 113 111 108 107 106 105 97 81 RELATIVE ACCURACY OF 256 DATA POINTS (%) 0.04 0.05 0.06 0.08 0.11 0.13 0.14 0.16 0.40 2.51 RELATIVE ACCURACY OF SINGLE CYCLE AT 60Hz (%) 0.23 0.20 0.17 0.16 0.16 0.16 0.16 0.16 0.28 1.26
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24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
MAX11040
Multiple Device Connection
Daisy chain up to eight MAX11040 devices for applications that require up to 32 simultaneously sampled inputs over a single SPI-/DSP-compatible serial interface with a single chip-select signal, and single interface commands that apply to all devices in the chain. The eight MAX11040 devices effectively operate as one device. There are two aspects to cascading multiple devices: the digital interface and the mechanism for keeping multiple devices sampling simultaneously. There are many configurations for connecting multiple devices; one is described in the next section, others are described in the Synchronizing Multiple Devices section within the Applications Information section.
n, which is driven by the CASCOUT of device n-1, allows device n to take over the SPI bus until all expected data is written or read; at this point, device n pulls its CASCOUT output low. Similarly, CASCOUT of device n drives CASCIN of device n+1. Figures 11 and 13 show read operations, including CASCIN and CASCOUT timings, for two cascaded devices and eight cascaded devices, respectively. The operation described above applies to all register operations except for writes to the Data Rate Control register. A fixed 16-bit word is written to the Data Rate Control registers of all devices in the chain, independent of the number of cascaded devices (see Figure 14). Reading from the Data Rate Control register returns 16 bits per cascaded device. Connecting the open-drain OVRFLW output of all devices together creates one signal that summarizes the overflow information of all devices. This is also true of the FAULT output. Connecting together these outputs from multiple devices has the effect of a "wire NOR." Any device that has an active condition on these outputs is allowed to pull the line low.
Multiple Device Digital Interface Figure 12 shows the most common way to daisy chain the digital interface of multiple devices. SPI bus arbitration is performed using CASCIN and CASCOUT. A falling edge at the CASCIN input of device
SYNC CS SCLK DIN
SYNC CS SCLK DIN
SYNC CS SCLK DIN
MAX11040
DSP OR MICROCONTROLLER CASCIN DRDYIN DEVICE 0 FAULT OVRFLW DOUT XIN XOUT CLKOUT XIN CASCOUT
MAX11040
CASCIN DRDYIN DEVICE n FAULT OVRFLW DOUT XIN CASCOUT
MAX11040
CASCIN DRDYIN DEVICE n+1 FAULT OVRFLW DOUT DRDYOUT
CASCADE UP TO 8 DEVICES
Figure 12. Daisy Chaining Multiple Devices
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24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
There are two ways to use a single line to indicate that all MAX11040s have their data ready, depending on whether or not they are clocked synchronously. If all MAX11040s have the same XIN clock and have been synchronized using SYNC or reset commands, the DRDYOUT of any device in the chain is used to represent all of them. Alternatively, if the devices use a different XIN clock, connect DRDYIN of device 0 to ground, and connect DRDYIN of device n to the DRDYOUT of device n-1 for all devices. DRDYOUT does not go low until DRDIN is low and the conversion of the device is complete. In this configuration, DRDYOUT of the last device goes low only when all devices in the chain have their data ready.
MAX11040
tCSW CS
DIN
SCLK
DOUT
DEVICE 0
DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 4
DEVICE 5
DEVICE 6
DEVICE 7
CASCOUT0 (CASCIN0 = 0)
CASCOUT1
CASCOUT2
CASCOUT3
CASCOUT4
CASCOUT5
CASCOUT6
CASCOUT7
Figure 13. Configuration Register Read Operation Timing Diagram for Eight Cascaded Devices
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24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
MAX11040
CS
DIN
B15 B14 B13 X
X B10 B9 B8
B7 B6 B5 B4 B3 B2 B1 B0
SCLK
DOUT
HIGH-Z
HIGH-Z
CASCOUT0 (CASCIN0 = 0)
CASCOUT1
CASCOUT2
CASCOUT3
CASCOUT4
CASCOUT5
CASCOUT6
CASCOUT7 X = RESERVED
Figure 14. Data Rate Controller Register Write Operation Timing Diagram for Eight Cascaded Devices
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24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
SYNC for Simultaneous Sampling with Multiple Devices The SYNC input permits multiple devices to sample simultaneously. The mismatch between the power-up reset of multiple devices causes the devices to begin conversion at different times. After a falling edge on the SYNC input, the device completes the current conversion and then synchronizes subsequent conversions (see Figure 15). Upon a SYNC falling edge, the MAX11040 measures the time between the SYNC falling edge to the preceding DRDYOUT falling edge, waits until the next DRDYOUT falling edge, then pauses the ADC for the measured amount of time. Figure 15 shows an example where the converter is regularly sampling the input and producing a DRDYOUT with a period tS. The effect of a SYNC falling edge as shown in Figure 15 is described in sequence below: 1) A SYNC falling edge is issued two XIN clock cycles after the DRDYOUT event 2. 2) The converter remembers the two XIN clock cycles, and completes the current sample, issuing DRDYOUT event 3 a period of tS after DRDYOUT event 2. 3) Then, the converter pauses for the remembered time period, two XIN clock cycles for this example. 4) Correspondingly, DRDYOUT event 4 is issued two XIN cycles later than it would have without the SYNC falling edge. 5) The process continues as normal with DRDYOUT event 5 appearing tS after DRDYOUT event 4.
MAX11040
NOTE: THE LATENCY IS NOT TO SCALE.
1 tS AIN_ 2
tS tS 3 4 tS
DELAY 2 CYCLES tS 5 6
tS XIN
tS
tS tS tS
DRDYOUT 1 2 3 4 5
SYNC MEASURE PAUSE
Figure 15. Effect of a SYNC Falling Edge
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25
24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
Referring back to the analog input, since the entire sampling section of the converter also paused for two clock cycles, the sampling point for sample 5 is also paused by two clock cycles, possibly creating a small disturbance at the SYNC falling edge. This disturbance is filtered with the digital filter, which makes it less distinct. If the SYNC falling edge occurred during the same XIN clock period as the DRDYOUT signal, the disturbance does not effect the periodic timing since the SYNC falling edge would demand a pause of zero XIN clock cycles. Hence, connecting the DRDYOUT of one converter to the SYNC inputs of many converters, as illustrated in Figure 12, aligns the sampling of the converters on the first SYNC falling edge, but does not disturb a regular sampling process for future samples. See the Multiple Device Synchronization section for different ways to use the SYNC input.
MAX11040
OUTPUT CODE FS = +0.88 x VREFIO 011...111 011..110 000...011 000...010 000...001 000...000 111...111 111...110 ZS = 0 -FS = -0.88 x VREFIO 1 LSB = 2(0.88 x VREFIO) FULL-SCALE TRANSITION
2N* *N = 19 FOR 19-BIT TRANSFER FUNCTION, N = 24 FOR 24-BIT TRANSFER FUNCTION
Transfer Function
Figures 16 shows the bipolar I/O transfer function. Code transitions occur halfway between successiveinteger LSB values. Output coding is binary, with 1 LSB = (0.88 x VREFIO) x 2/524,288 in 19-bit mode and 1 LSB = (0.88 x VREFIO) x 2/16,777,216 in 24-bit mode.
100...001 100...000 -FS 0 DIFFERENTIAL INPUT VOLTAGE (LSB) FS FS - 3/2 LSB
Power-On Reset
The serial interface, logic, digital filter, and modulator circuits reset to zero at power-up. The power-on reset circuit releases this reset no more than 1ms after VDVDD rises above 2V.
Figure 16. ADC Transfer Function
26
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24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
Applications Information
Multiple Device Synchronization
Synchronizing Multiple Devices Using a Shared XIN Clock Source To synchronize multiple devices sharing a single XIN clock source, transition the SYNC input that is shared by all devices high to low. When an external sync source is not available, connect DRDYOUT of one MAX11040 to the SYNC input of all devices in the chain. The MAX11040 ignores any SYNC transitions applied during the power-on reset. Synchronizing Multiple Devices Using Independent XIN Clock Sources If it is undesirable to connect the XIN clock sources together, due to EMI or other reasons, use DRDYIN, DRDYOUT, and SYNC to align the conversion timing as shown in Figure 17. This minimizes the effects of drift
between the clock sources by resynchronizing after each conversion when DRDYOUT transitions low. In this configuration, the maximum correction caused by a SYNC edge is one XIN clock cycle. The resulting sampling rate is determined by the sampling frequency of the device with the slowest clock source, plus the delay through the DRDYIN to DRDYOUT chain between this slowest device and the end of the chain.
MAX11040
Synchronizing Multiple Devices to an Independent Clock Source To periodically synchronize multiple devices to an independent timing source, connect the timing source to the SYNC inputs of the devices. If minimal jitter is important in the application, program the MAX11040's to a frequency slightly slower than the external frequency, such that SYNC falling edges only occur a short time after the DRDYOUT signals.
SYNC CS SCLK DIN
SYNC CS SCLK DIN
SYNC CS SCLK DIN
MAX11040
DSP OR MICROCONTROLLER CASCIN DRDYIN CASCOUT DRDYOUT DEVICE 0 FAULT OVRFLW DOUT XIN XOUT CLKOUT XIN
MAX11040
CASCIN DRDYIN CASCOUT DRDYOUT DEVICE n FAULT OVRFLW DOUT XOUT XIN
MAX11040
CASCIN DRDYIN DEVICE n+1 FAULT OVRFLW DOUT XOUT DRDYOUT
CASCADE UP TO 8 DEVICES
Figure 17. One Crystal per MAX11040 and All SYNC Inputs Driven by DRDYOUT of the Last Device in the Chain
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27
24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
Signal Distortion at SYNC Falling Edges Each SYNC falling edge causes a disruption in the digital filter timing proportional to the delay from the previous falling edge of DRDYOUT to the falling edge of SYNC. Any analysis of the output data that assumes a uniform sampling period sees an error proportional to that delay, with a maximum value determined by the maximum derivative of the analog input. Figure 18 shows the effect of this discontinuity at output sample 5. Assuming a 60Hz 2.2V sine wave, the maximum possible error on any given sample caused by a SYNC falling edge is: VERROR_MAX = 2.2V x 2 x 60Hz x tDRDYOUT_TO_SYNC = 0.83V/ns x tDRDYOUT_TO_SYNC The delay from DRDYOUT to SYNC is quantized to within one cycle of the 24.576MHz clock. SYNC pulses that are asynchronous to DRDYOUT may cause large errors. To eliminate this error, use a single clock source for all devices and avoid disrupting the output data timing with SYNC pulses while making high-precision measurements. Alternately, minimize the delay from DRDYOUT to SYNC to minimize the error.
MAX11040
Example: Assume f AIN_ = 60Hz, f S = 16ksps, and eight total devices in the chain. Device 1 has the longest tDRDYOUT_TO_SYNC delay, therefore the worst-case SYNC error. If device 1 has the fastest XIN clock in the chain, and device 2 has the slowest XIN clock in the chain, and they differ by 0.1%, device 1 completes its conversion as much as 0.1% earlier than device 2. Hence, the delay of device 2 is: 0.1% x (1/16kHz ) = 62.5ns The signal then propagates down the chain at a time delay of nominally 20ns for each device. The total delay back to the SYNC falling edge after going through six additional delays is: tDELAY = 62.5ns + 6 x 20ns = 182.5ns Maximum % Error = 2 x fIN x tDRDYOUT_TO_SYNC x 100% = 2 x x 60Hz x 182.5ns x 100% = 0.007% The above error is relative to the signal level, not to the full scale of the data converter.
NOTE: THE LATENCY IS NOT TO SCALE. tS 1 2 AIN_ 3 4 5 tS tS tS tS 6 tS tS tS tDRYOUT_TO_SYNC tS
DRDYOUT
1
2
3
4
SYNC PAUSE FOR tDRYOUT_TO_SYNC
MEASURE tDRYOUT_TO_SYNC 1 RECONSTRUCTED DIGITAL OUTPUT 2 3
4 DISCONTINUITY DUE TO SYNC EVENT 5 6
Figure 18. Example of Discontinuity in Reconstructed Digital Output Due to SYNC Falling Edge with a Large DRDYOUT-to-SYNC Delay
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24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
Source Impedance and Input Sampling Network
The source impedance that drives the analog inputs affects the sampling period.
Analog Filtering
The analog filtering requirements in front of the MAX11040 are considerably reduced compared to a conventional converter with no on-chip filtering. The internal digital filter has significant rejection of signals higher than the Nyquist frequency of the output data rate that would alias back into the sampled signal. The internal digital filter does not provide rejection close to the harmonics of the 3.072MHz modulator frequency. For example, assuming an output data rate of 16ksps if the XIN clock is set to 24.576MHz, then the band between 3.0686MHz and 3.0750MHz is not explicitly filtered. Since this unfiltered band is very small compared to its actual frequency, very little broadband noise enters through this mechanism. If focused narrowband noise in this band is present, a simple analog filter can create significant attenuation at this frequency because the ratio of passband to stopband frequency is large. In addition, because the device's common-mode rejection extends out to several 100kHz, the common-mode noise susceptibility in this frequency range is substantially reduced. Providing additional filtering in some applications ensures that differential noise signals outside the frequency band of interest do not saturate the analog modulator. The modulator saturates if the input voltage exceeds its full scale (2.2V). The digital filter does not prevent a large signal in the filter stopband from saturating the modulator. If signals outside the band of interest cause violation of this full scale while accurate conversion of passband signals is desired, then additional analog filtering is required to prevent saturation.
MAX11040
Low-Impedance Sources Minimize the source impedance to ensure the input capacitor fully charges during the sampling phase. The required source resistance is defined by the equation below:
RSOURCE _ MAX < tSAMP 1 K x CSAMP x In Error 120ns 1 1.5 x 4pF x In Error
- RINT
=
- 2600
where K = 1.5 and RINT = 2600. For example, the required source resistance to achieve 0.1% accuracy is: 120ns RSOURCE _ MAX < - 2600 1 1.5 x 4pF x ln 0.1% = = 120ns - 2600 1.5 x 4pF x ln(1000) 120ns - 2600 = 294 1.5 x 4pF x 6.91
High-Impedance Sources If the source impedance is greater than R SOURCE_MAX , as defined in the Low-Impedance Sources section, place a 0.1F bypass capacitor between AIN_+ and AIN_- to provide transient charge. The average switched-capacitor load with a proper bypass capacitor and XIN clock frequency = 24.576MHz is equivalent to a 130k resistor connected between AIN_+ and AIN_-. This resistance is independent of the value of the 0.1F bypass capacitor. If another XIN clock frequency is chosen, this resistance is directly proportional to the XIN clock period. Although the addition of a bypass capacitor helps charge the MAX11040 input capacitor, some gain error due to resistive drop across the source resistance still remains. Calculate this gain error using the following equation:
Gain = RSOURCE RSOURCE = RSOURCE + RLOAD RSOURCE + 130k
Compensating for the Rolloff of the Digital Filter in Typical FFT Analysis
To calculate FIR_GAIN(fAIN_): 1) Decide the number of evenly spaced frequencies between DC and the Nyquist frequency of the output data rate at which correction factors are desired, which is usually the same as the FFT result. 2) Create an array with a length that is 2x the number of the desired frequencies. (Again, the result is likely to correlate with the time domain array that is loaded into an FFT algorithm.) 3) Fill this array with the filter coefficients provided in the Digital Filter section. Fill the rest of the array with zeros. 4) Take an FFT of this array. The result represents the response of the MAX11040 built-in FIR filter.
29
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24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
MAX11040
To compensate the result of an FFT for the MAX11040 output data: 1) Calculate the inverse (1/x) of the equation provided in the Digital Filter section for each frequency in the FFT. 2) Multiply the FFT of the MAX11040 output data by the result of the above step.
Layout the traces in perpendicular directions when a digital line and an analog line cross each other. Bypass AVDD to the analog ground plane with a 0.1F capacitor in parallel with a 1F to 10F low-ESR capacitor. Keep capacitor leads short for best supply-noise rejection. Bypass REF+ and REF- with a 0.1F capacitor to GND. Place all bypass capacitors as close as possible to the device for optimum decoupling.
Power Supplies
AVDD and DVDD provide power to the MAX11040. The AVDD powers up the analog section, while the DVDD powers up the digital section. The power supply for AVDD and DVDD ranges from +3.0V to +3.6V and 2.7V to VAVDD, respectively. Bypass AVDD to AGND with a 1F electrolytic capacitor in parallel with a 0.1F ceramic capacitor and bypass DVDD to DGND with a 1F electrolytic capacitor in parallel with a 0.1F ceramic capacitor. For improved performance, place the bypass capacitors as close as possible to the device.
Crystal Layout
Follow these basic layout guidelines when placing a crystal on a PCB with a MAX11040 to avoid coupled noise: 1) Place the crystal as close as possible to XIN and XOUT. Keeping the trace lengths between the crystal and inputs as short as possible reduces the probability of noise coupling by reducing the length of the "antennae." Keep the XIN and XOUT lines close to each other to minimize the loop area of the clock lines. Keeping the trace lengths short also decreases the amount of stray capacitance. 2) Keep the crystal solder pads and trace width to XIN and XOUT as small as possible. The larger these bond pads and traces are, the more likely it is that noise will couple from adjacent signals. 3) Place a guard ring (connect to ground) around the crystal to isolate the crystal from noise coupled from adjacent signals. 4) Ensure that no signals on other PCB layers run directly below the crystal or below the traces to XIN and XOUT. The more the crystal is isolated from other signals on the board, the less likely for noise to couple into the crystal. 5) Place a local ground plane on the PCB layer immediately below the crystal guard ring. This helps to isolate the crystal from noise coupling from signals on other PCB layers. Note: Keep the ground plane in the vicinity of the crystal only and not on the entire board.
Layout, Grounding, and Bypassing
The best layout and grounding design always comes from a thorough analysis of the complete system. This includes the signal source's dependence and sensitivity on ground currents, and knowledge of the various currents that could travel through the various potential grounding paths. Use PCBs with separate analog and digital ground planes. Connect the two ground planes together only at the MAX11040 GND input. Isolate the digital supply from the analog with a low-value resistor (10) or ferrite bead when the analog and digital supplies come from the same source. Ensure that digital return currents do not pass through the analog ground and that return-current paths are low impedance. A 5mA current flowing through a PCB ground trace impedance of only 0.05 creates an error voltage of approximately 250V. Ensure that digital and analog signal lines are kept separate. Do not run digital (especially the SCLK and DOUT) lines parallel to any analog lines or under the MAX11040.
Chip Information
PROCESS: BiCMOS
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24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
Pin Configuration
TOP VIEW
AIN0- 1 AIN0+ 2 REF0 3 AGND 4 AIN1- 5 AIN1+ 6 REF1 7 AGND 8 REFIO 9 AGND 10 DGND 11 DVDD 12 CASCIN 13 CASCOUT 14 CS 15 SCLK 16 DIN 17 DOUT 18 FAULT 19
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 38 TSSOP PACKAGE CODE U38+2 DOCUMENT NO. 21-0081
MAX11040
+
38 AIN237 AIN2+ 36 REF2 35 AGND 34 AIN333 AIN3+
MAX11040
32 REF3 31 AGND 30 AVDD 29 AGND 28 DGND 27 DVDD 26 XIN 25 XOUT 24 SYNC 23 DRDYIN 22 DRDYOUT 21 CLKOUT 20 OVRFLW
TSSOP
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24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC
MAX11040
Revision History
REVISION NUMBER 0 1 2 REVISION DATE 5/09 4/10 6/10 Initial release Corrected equation in Digital Filter section Changed gain-error drift in Electrical Characteristics section DESCRIPTION PAGES CHANGED -- 11 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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